TSMC revealed additional details about its N2 (2nm-class) fabrication process at the IEEE International Electron Device Meeting (IEDM) earlier this month. The new production node promises a 24 to 35% power reduction or 15% performance improvement at the same voltage, and 1.15X higher transistor density than the prior-gen 3nm process. The vast majority of these advantages are enabled by TSMC's new gate-all-around (GAA) nanosheet transistors along with N2 NanoFlex design-technology co-optimization capability and some other enhancements detailed at IEDM.
Gate-all-around nanosheet transistors allow designers to adjust their channel width to balance performance and power efficiency. On top of that, TSMC's N2 adds N2 NanoFlex DTCO, enabling designers to develop short cells with minimum area and enhanced power efficiency, or tall cells optimized for maximum performance. The technology also includes six voltage threshold levels (6-Vt) spanning a 200mV range, achieved using TSMC's third-generation dipole-based integration with both n-type and p-type dipoles.
