TSMC exposed the defect density (D0) of its N2 process technology relative to its predecessors at the same stage of development at its North American Technology Symposium this week. According to the company, the defect density is below that of N3, N5, and N7 manufacturing nodes. In addition, the slide published by ComputerBase reveals that N2 is two quarters away from mass production, which means that TSMC is on-track to start making 2nm-class chips in late Q4 2025, as expected.
Although TSMC's N2 is the company's first process technology to adopt gate-all-around (GAA) nanosheet transistors, the node has lower defect density than its predecessors at the same stage of development, two quarters before mass production (MP). The predecessors — N3/N3P, N5/N4, and N7/N6 — all relied on well-known FinFET transistors. So, despite being TSMC's first node using GAA nanosheet transistors, the N2 defect density is getting lower quicker (well, steeper) than that of its predecessors before the high volume manufacturing (HVM) milestone.
