Samsung researchers have published a detailed account of an experimental NAND architecture that aims to cut one of the technology’s largest power drains by as much as 96%.
The work — Ferroelectric transistor for low-power NAND flash memory — was carried out by researchers at the Samsung Advanced Institute of Technology and appears in the journal Nature. It describes a ferroelectric field-effect transistor (FeFET) design intended for future 3D NAND, combining a hafnia-based ferroelectric with an oxide-semiconductor channel and introducing a near-zero pass-voltage operation that forms the basis of the 96% power reduction figure.
