
One of the many Zen 5 architectural changes announced at AMD's Ryzen 9000 Computex keynote was the architecture's bandwidth doubling of the L1 and L2 caches. HLX on X (formally Twitter) discovered an Aida64 benchmark run of a Ryzen 5 9600X engineering sample, confirming AMD's L1 and L2 cache tweaks.
The Aida64 benchmark reveals that the Ryzen 5 9600X offers almost 3,800 GB/s of read bandwidth on the L1 cache. Write bandwidth was rated at nearly 1,900 GB/s, and copy speed was tested at almost 3,800 GB/s, just like the read speed, all with a blazing sub-1 nanosecond cache latency, which we would expect from a first-level cache.