Rapidus has successfully begun installing ASML's Twinscan NXE:3800E EUV lithography system at its Innovative Integration for Manufacturing (IIM-1) facility in Chitose, Hokkaido, marking a significant milestone for Japan’s semiconductor industry. In 2025, the tool will be used to make prototype chips using a 2nm process technology and then for commercial semiconductor production starting in 2027.
ASML's Twinscan NXE:3800E lithography system is currently the company's most advanced lithography tool explicitly designed to produce chips at 2nm-class process technologies and beyond. The machine features ASML's latest high-power light source, a new wafer handler, faster wafer stages, and other components needed to support increased throughput, enabling the performance of over 220 wafers per hour at a 30 mJ/cm² dose.
The system — which weighs 71 tonnes and stands 3.4 meters tall — must be assembled in four stages. Rapidus expects to conclude installation by the end of the month (according to Nikkei) and set a new milestone for Japan's semiconductor industry, as this is the country's first EUV machine intended to produce logic chips using EUV-based process technologies.
Rapidus's IIM-1 plant is set to begin pilot operations in April 2025. The pilot line will implement a single-wafer processing system across all production stages, which will help the company's engineers and fab workers better understand how each tool works and adjust the manufacturing process accordingly. Thus, lower defect densities (and, therefore, better yields on test wafers) will be achieved faster.
Rapidus has partnered with IBM to develop its 2nm-class process technology for logic chips that rely on gate-all-around transistors. The company hopes to start mass production of 2nm semiconductors by 2027, putting it 1.5–2 years behind Intel and TSMC, which are set to begin commercial production of 1.6nm and 2nm-class chips in the second half of 2025. While this may not sound like a breakthrough for a chip contract manufacturer, it will be a major breakthrough for the Japanese semiconductor industry.
Rapidus also plans to offer its customers a "secret sauce" for advanced chip packaging services. First, Rapidus will package chips in the same fab where it will produce them. Second, Rapidus aims to automate chip packaging, thus shrinking cycle times. In contrast to the highly automated front-end lithography process, back-end production remains labor-intensive. While this reliance on manual work allows for some adaptability, it also limits production speed.
Existing advanced packaging facilities still have not fully implemented automation either. By introducing automation to this stage, Rapidus aims to significantly enhance the efficiency and pace of chip packaging, which it hopes will be a critical improvement as advanced packaging technologies become increasingly intricate. Additionally, the company is working closely with several Japanese suppliers to procure materials needed for back-end operations, which will boost the local semiconductor industry.
Rapidus's Innovative Integration for Manufacturing (IIM-1) facility will cost around $32 billion when fully built and equipped, but the company must still secure funding. Japanese banks are reluctant to provide money to a company with no track record.
