TSMC is developing a new version of its Chip-On-Wafer-On-Substrate-L (CoWoS-L) that will enable it to build extremely large interposers — which it calls Super Carrier Interposers — that pushing the boundaries of current system-in-package (SiPs) sizes to levels never seen before. The next-generation CoWoS technology, planned to be qualified in 2025, will potentially increase the size of interposers up to six reticle sixes, up to 3.3 times what they can do today.
This push for larger chip sizes is driven by the increasing global demand for advanced computing capabilities in applications like artificial intelligence (AI) and high-performance computing (HPC). Major players like AMD, Intel, and Nvidia, are responding to this demand by building highly-complex processors, such as Nvidia's H100, that sell for some $30,000 per unit.
