The PCI-SIG consortium has officially announced the development of the PCI Express 8.0 specification. This new version is set to double data transfer rate to 256 GT/s per lane. In addition to the extra bandwidth, PCIe Gen8 is said to feature protocol enhancements to increase real-world bandwidth and reduce power consumption.
The upcoming PCIe 8.0 specification will double the raw bit rate of PCIe 7.0 to 256.0 GT/s, enabling up to 1 TB/s of bi-directional bandwidth across a x16 configuration. The spec will continue to rely on PAM4 signaling with forward error correction (FEC) and Flit Mode encoding, which have been used with PCIe 6.0 and PCIe 7.0. However, hitting 256 GT/s per lane will likely be an incredibly difficult task. Engineers will enter uncharted territory, as no current copper interconnect standard can boast such a data transfer rate, especially over distances of tens of centimeters.
