Nvidia's Vice-president and General Manager of HPC-geared DGX systems has come forward to set the record state on where exactly the company's GPU volume issues lie. According to Boyle, the problem doesn't come from Nvidia miscalculating demand or wafer yield issues at its manufacturing partner, TSMC.
Instead, the bottleneck in manufacturing enough GPUs that can cater to both consumer and professional workloads (looking at you, AI boom) lies with the chip packaging steps that come after. Nvidia's H-class GPUs make use of TSMC's 2.5D Chip-on-Wafer-on-Substrate (CoWoS) packaging technology, a multi-step, high-precision engineering step whose complexity slows down the number of GPUs that can be assembled in a given timeframe. This can disproportionately impact supply; the delta between the number of GPUs required and those available even led Elon Musk to say they were proving "harder to acquire than drugs." We couldn't check that here at Tom's Hardware, but we'll trust Mr. Musk to know that one after Twitter/X procured as many as 10,000 of Nvidia's compute-focused GPUs.
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