A research team at Kyoto University has built a silicon carbide (SiC) transistor that operates at 600°C (873 K) using ion implantation, the doping step used across commercial chip fabs, and cut the gap between its designed and measured threshold voltage to under 0.1V at 400°C, down from more than 2V in the conventional layout. The work, announced earlier this month by Mitsuaki Kaneko, Shunya Shibata, and Tsunenobu Kimoto and published in APL Electronic Devices, pairs a bottom-gate transistor with a double-well isolation structure to keep an ion-implanted SiC junction field-effect transistor stable at temperatures where silicon stops working above roughly 250°C.
The bottom-gate layout puts the gate electrode beneath the channel, which captures the dopants that scatter deeper than intended during implantation, a channeling effect that had thrown conventional top-gate JFET thresholds off by more than 2V. With the channeling tail compensated, the design-to-measured threshold voltage gap dropped to under 0.1V at 400°C.