Intel Foundry this week released a promotional document aimed at detailing its leading-edge front-end and back-end offerings for AI and HPC applications, and showcased its 'AI chip test vehicle' that demonstrates the company's current packaging capabilities. Indeed, they are quite impressive as the company is showing off an 8 reticle-sized system-in-package (SiP) that features four logic tiles, 12 HBM4-class stacks, and two I/O tiles. More importantly, unlike the massive concept with 16 logic tiles and 24 HBM5 stacks the company presented last month, this one is actually manufacturable today.
First and foremost, it is necessary to note that what Intel Foundry is showcasing is not a working AI accelerator, but rather an 'AI chip test vehicle' that shows how future AI and HPC processors can be physically built (or rather assembled). To a large degree, the company is demonstrating its entire construction method that combines large compute tiles, stacks of high-bandwidth memory, ultra-fast chip-to-chip links, and a new class of power delivery into one manufacturable package. This package differs significantly from what TSMC offers today (more on this later). In short, the concept shows that next-generation heavy-duty AI processors are multi-chiplet designs, and Intel Foundry can build them.
