Intel disclosed several chip packaging breakthroughs at the Electronic Components Technology Conference (ECTC), outlining the technical merits of multiple new chip packaging techniques. We spoke with Dr. Rahul Manepalli, an Intel Fellow and VP of Substrate Packaging Development, for more details on three of the new packaging technologies: EMIB-T for boosting both the size of chip packages and power delivery capabilities to support new technologies like HBM4/4e, a new disagregated heat spreader design, and a new thermal bonding technique that improves reliability, yields, and enables scaling to finer chip-to-chip connections. Intel also participated in 17 other new papers presented at the event.
Intel Foundry aims to produce chips for both Intel's own internal use and for external companies, utilizing leading-edge process node technology. However, modern processors are increasingly deployed with complex, heterogeneous designs that integrate multiple types of computing and memory components into a single chip package, thereby amplifying performance, cost, and power efficiency gains. These chip designs rely upon increasingly complex advanced packaging techniques that serve as the bedrock of heterogeneous designs, so continued evolution is critical as Intel keeps pace with competitors like TSMC.
