In 2017, imec introduced its forksheet transistor as a natural extension to gate-all-around (GAA) transistors. However, according to a recent announcement by imec at the VSLI Symposium 2025, there have been doubts about its manufacturability in high volumes. To address these concerns, the research giant has developed a new approach to bleeding-edge forksheet transistor design, which will enable the future of transistors to continue advancing.
Researchers from imec introduced a new transistor layout named 'outer wall forksheet', which they expect to be used starting from the A10 generation (1nm, 10 Angstroms) all the way to the A7 generation, according to a new imec paper.
