Anirudh Devgan, the CEO of Cadence, recently remarked that the company's AI-assisted chip design tools enable chip performance and density benefits similar to the transition to a next-generation process node, but without moving to a new node. Devgan cited strong performance, power, and area (PPA) improvements, the most important metrics for chipmakers (along with cost), and also cited drastic improvements in productivity and examples with the company's own custom processors.
Discussing the EDA company's latest suite of AI-assisted software tools, Devgan said, "So, overall, we are pleased with the benefit we are getting, especially with the improvement in PPA. And productivity improvements can be anywhere between 5x to 10x, but the PPA benefits are truly remarkable and almost equivalent to one kind of node. One process node migration typically gets [s] 15% to 20% PPA improvement, and we can get that with AI."
"As you may know, we have five major AI platforms [in the Cadence.AI portfolio], analog, digital, verification, PCB and package and system analysis, it is a pretty rich portfolio," said Anirudh Devgan, chief executive of Cadence, during the company's earnings conference call with analysts and investors (via SeekingAlpha). "The customers are routinely seeing anywhere from 5% to 20% improvement in PPA, which is significant."
Modern process technologies give fairly limited node-to-node performance and transistor density scaling. Compared to TSMC's N5 (a 5nm-class process technology), the company's N3 (a 3nm-class node) offers a 10% to 15% performance improvement, and TSMC promises a similar enhancement for N2 compared to N3. Therefore, getting up to a 20% performance boost by just using a set of AI-optimized tools is a very significant achievement akin to a step forward to a new node.
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