In a rather unexpected turn of events, AMD announced late on Monday that it had obtained its first 2nm-class silicon, a core complex die (CCD) for its 6th Generation EPYC 'Venice' processor, which is expected to launch next year. The Venice CCD is the industry's first HPC CPU design to be taped out on TSMC's N2 process technology, highlighting AMD's aggressive roadmap and the readiness of TSMC's production node.
AMD's 6th Generation EPYC 'Venice' is expected to be based on the company's Zen 6 microarchitecture and is expected to be launched sometime in 2026. The CPU will rely on CCDs to be made on TSMC's N2 (2nm-class) fabrication process, so it is about time for the company to get the first Venice CCDs out of the fab. Yet, the fact that AMD already has chips it can talk about highlights the long-standing collaboration between AMD and TSMC as well as the culmination of joint efforts to build chips on one the most advanced process technologies that TSMC has ever developed to date.
