Specifications for AMD's next-generation Zen 6-based server products have surfaced at Baidu, via HXL at X. Venice, the successor to AMD's current Turin server offerings, will reportedly pack as many as 256 cores based on the Zen 6c design, suggested with 1GB of total L3 cache, and that's without any additional 3D cache chiplets. We must tread with caution and not treat these details as definitive, since these products are likely a year or more away from launch.
AMD's current-generation Zen 5-based server EPYC 9005 CPUs, codenamed Turin, slot into the SP5 socket, similar to EPYC 9004 (Genoa), which used Zen 4 cores, adopting a design similar to Arm's big.LITTLE. AMD also launched these CPUs with denser Zen 4c/5c cores, with Turin Dense reaching up to 192 cores/384 threads. Similarly, AMD also offers the cost-effective SP6 socket, which currently supports AMD's EPYC 8004 (Siena) offerings with up to 64 Zen 4c cores, also rumored to be compatible with the speculated Zen 5-based EPYC 8005 (Sorano) family.
