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Tom’s Hardware
Tom’s Hardware
Technology
Anton Shilov

UCIe 2.0 specifications standardize management architecture and 3D packaging across different chiplets

Architecture Intel Corporation
Intel.

The UCIe Consortium on Wednesday released version 2.0 of the UCIe specification, which brings support for standardized management of system architecture across different chiplets and support for industry-standard 3D packaging of chiplets with hybrid bonding and bump pitches of variable sizes. The new specification makes it easier to develop, build, and manage system-in-packages (SiP) containing chiplets from different vendors. 

For now, SiPs with UCIe chiplets have to use multiple management frameworks for each chiplet if they use chiplets from more than one vendor. The UCIe 2.0 specification introduces a standardized manageability system architecture that addresses manageability, testability, and debugging (Dfx) across multiple chiplets throughout the SiP lifecycle. In addition, the new spec defines optional UCIe DFx Architecture (UDA), which integrates vendor-agnostic testing, telemetry, and debug fabric within each chiplet to simplify development and bring-up of multi-chip system-on-packages.

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