The race is on to build the massive chip packages that power the future of AI, with some technologies being developed to produce a single chip that houses a monstrous 58 chips in one unit. But the future pathway to those sorts of massive chips isn't entirely agreed upon yet, as learned at TSMC's recent European Technology Symposium that we attended.
Although panel-level packaging technologies are set to enable much larger chip packages, they will not provide, at least initially, the same interconnection densities as today's wafer-level packaging technologies like CoWoS, according to Kevin Zhang, TSMC’s senior vice president of business development and global sales and deputy co-COO.
