Backside power delivery network (BS PDN) for next-generation chips is a well-known and widely discussed advantage of future process technology. While Intel and TSMC have talked about BSPDN for a while, Samsung only recently shared details about its backside power delivery experiments. It appears the company expects quite noticeable advantages from this innovation.
In a paper presented at the VLSI Symposium in late June, Samsung Electronics reported that the application of a backside power delivery network resulted in a 14.8% reduction in the area of an undisclosed processor compared to the traditional frontside PDN, reports The Elec (via @harukaze5719). Meanwhile, the paper specifically highlighted two Arm circuits, where they observed area reductions of 10.6% and 19%, respectively. A 10% to 19% die area reduction is a major advantage as it enables one to either pack 10% to 19% more transistors and gain performance or reduce the costs of a given chip.
