The PCI-SIG, the organization that oversees development of PCIe and adjacent standards, on Wednesday announced the availability of the PCIe 8.0 draft specification version 0.5, a major milestone. The first draft of the specification sets the architectural requirements and is designed to enable PCI-SIG members to start prototyping and submit their final proposals. Version 0.5 of the specification maintains that the transfer rate supported by the new interconnection will reach 256 GT/s, enabling up to 1 TB/s bi-directional bandwidth via an x16 configuration.
Version 0.5 of the PCIe standard is the first full draft of the spec that locks in key conceptual targets and mechanisms, and outlines all major aspects of the architecture, including electrical, logical, compliance, and software. This means that PCI-SIG maintains a target bit rate of 256 GT/s; PAM4 signaling with forward error correction (FEC) and Flit Mode encoding; bandwidth-improving protocol enhancements; backward compatibility; and new connector technology that is now being evaluated. Meanwhile, since version 0.5 is not the final draft and not all parts of the specification are frozen, some electrical parameters and protocol optimizations can be tuned further.
