PCI-SIG on Tuesday published version 0.3 of the PCI Express 7.0 specification, marking a significant achievement for the technology that will increase the PCIe data transfer rate to 128 GT/s. This preliminary release indicates that members of the organization have agreed on the key features and architecture of the upcoming technology.
PCIe 7.0 is set to enhance the data transfer speed to 128 GT/s for each pin, substantially improving the 64 GT/s in PCIe 6.0 and the 32 GT/s in PCIe 5.0. This implies a 16-lane (x16) connection can support a bi-directional bandwidth of 512 GB/s before considering the encoding overhead. In a bid to increase data transfer rate and bandwidth, the PCIe Gen7 interface is set to use pulse amplitude modulation with four levels (PAM4) signaling, 1b/1b flit mode encoding, and forward error correction (FEC), which are features that the standard inherits from PCIe Gen6.
