It's not slated to arrive anytime soon, but a P-core architecture that Intel is working on will purportedly boast big IPC improvements, as well as support Intel's new APX instruction set. This information was discovered by INstLatX64 on X.
According to a user on the real world technologies forum, Panther Cove will represent a big architectural overhaul of Intel's P-core design, featuring "large IPC" improvements as well as support for Intel's APX and AVX10 standards. Panther Cove is one of the furthest out architectures Intel is purportedly working on, and is purportedly expected to arrive after Cougar Cove, which is itself slated to land after Lion Cove, a P-Core architecture powering Core Ultra 200 series Lunar Lake and Arrow Lake CPUs.
According to @SShwartsman's post on @rwt, #Intel #APX will be supported in #PantherCove core.It seems that it's no coincidence that #DiamondRapids (CPUID 400F10) is no longer a member of Fam6...https://t.co/dZppDKHerM https://t.co/urk3xIVqR2 pic.twitter.com/JvAULqg4IlSeptember 29, 2024
The forum user notes that Intel's development strategy with its P-core architectures harkens back to its "tick-tock" architectural development the company was known for during the 2010s where one major architectural change was succeeded by one minor architectural update before the cycle restarts for the next architecture design.
As a result, the forum user discloses that Cougar Cove will be an update "tock" of Lion Cove that we have right now with Lunar Lake and Arrow Lake. Panther Lake will be the next major "tick" in Intel's architectural cycle, which would explain the claims about big IPC improvements.
The most interesting tidbit about Panther Cove is the addition of Intel APX. APX stands for Intel Advanced Performance Extensions and serves as an extension of the entire x86 instruction set. According to Intel, APX adds more registers and various new features that improve general-purpose performance, without significantly increasing power consumption or silicon area.
Specifically, APX doubles the amount of general-purpose registers from 16 to 32, which allows the compiler to keep more values in registers. APX also adds new conditional forms of load, store, and compare/test instructions to help offset the performance issues of out-of-order CPUs, which take advantage of branch predictors. These conditional forms purportedly cut down on the number of branches that may incur misprediction penalties.
It is unknown what CPU architecture Panther Cove will reside in, but if Intel's timeline stays consistent, we could see Panther Cove in the Core Ultra 400 series.
