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The Hindu
The Hindu
National
Special Correspondent

IISc researchers develop design framework for next generation analog chipsets

Researchers at the Indian Institute of Science (IISc) have developed a design framework to build next-generation analog computing chipsets that could be faster and require less power than the digital chips found in most electronic devices.   

Using a novel design framework, the team has built a prototype of an analog chipset called ARYABHAT-1 (Analog Reconfigurable technologY And Bias-scalable Hardware for AI Tasks). This type of chipset can be especially helpful for Artificial Intelligence (AI)-based applications like object or speech recognition – like Alexa or  Siri – or those that require massive parallel computing operations at high speeds, an IISc release said.

Most electronic devices use digital chips because the design process is simple and scalable. “But the advantage of analog is huge. You will get orders of magnitude improvement in power and size,” explained Chetan Singh Thakur, Assistant Professor at the Department of Electronic Systems Engineering (DESE), IISc, whose lab is leading the efforts to develop the analog chipset. In applications that don’t require precise calculations, analog computing has the potential to outperform digital computing as the former is more energy-efficient.  

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