Hardware researcher spins up 'CPU deoptimization' project to find the slowest single x86 instruction, creates hall of shame — worst offender takes 198 billion cycles spanning 62 seconds to execute

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To optimize how software runs on hardware, instruction latency analysis looks at the time it takes for low-level instructions to execute on a processor, either to optimize the architecture or to optimize applications to run on a particular architecture. One hardware researcher, Christopher Domas (@xoreaxeaxeax on GitHub), is taking a different approach with the CPU Deoptimization leaderboard, which looks not to make Assembly instructions run as fast as possible, but as slow as possible to measure the single instruction with the highest latency.

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