Fujitsu has demonstrated a mechanical sample of its Armv9-based 144-core Monaka processor for data centers, revealing some details. Less than a week ago, it disclosed that it is being developed with Broadcom and relies on its 3.5D eXtreme Dimension System in Package platform. Satoshi Matsuoka, director of the RIKEN Center for Computational Science (R-CCS) and a professor at Tokyo Tech, published the image.
Fujitsu's Monaka is a huge CoWoS system-in-package (SiP) that has four 36-core compute chiplets made on TSMC's N2 process technology housing 144 Armv9-based cores with enhancements that are stacked on top of SRAM tiles in a face-to-face (F2F) manner using hybrid copper bonding (HCB). The SRAM tiles (essentially huge caches) are produced on TSMC's N5 process technology. The compute and cache stacks are accompanied by a relatively colossal I/O die that integrates a memory controller, PCIe 6.0 lanes with CXL 3.0 on top to connect accelerators and extenders, and other interfaces that one comes to expect from a datacenter-grade CPU.
