Peking University's School of Integrated Circuits has unveiled a prototype electronic design automation (EDA) tool built specifically for Huawei's LogicFolding architecture, according to the South China Morning Post. The tool takes what researchers described as a "true-3D" approach, optimizing an entire multilayer chip as a single vertical structure rather than designing each layer in two dimensions and stacking them afterward. In early tests of open-source circuit designs, the university reported a 30% reduction in total internal wire length, along with improvements in performance and thermal management, compared to conventional EDA workflows.
The announcement came two days after Huawei presented LogicFolding and its accompanying Tau Scaling Law at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai. Huawei's goal is to produce chips with transistor density equivalent to 1.4nm processes by 2031, all without access to the extreme ultraviolet (EUV) lithography equipment restricted under U.S. export controls.
