Cadence Design Is Cementing Its Place in the 2nm AI Chip Race By Solving the Die Size Limit in Partnership With a Major Chipmaker

Cadence Design Systems (CDNS) has just announced a multi-year partnership with Samsung Foundry to provide chipmakers a fully certified production-ready design platform for building next-generation AI chips. The collaboration targets Samsung’s 2nm process, combining it with Cadence’s 3D-IC design support. As artificial intelligence pushes the limits of the performance that can be squeezed out of a single die, chipmakers have started stacking multiple dies vertically to pack more compute and memory into a single package. The technique, also known as 3D-IC, requires the right EDA tools and IP blocks, which Cadence will now provide to Samsung.

It is worth noting that this partnership also involves integration of Nvidia’s (NVDA) NVLink-C2C technology, which links the GPUs and CPUs to high-bandwidth memory, a must-have for AI workloads. Through this, Nvidia is acting as a technology enabler rather than just an end customer later on. Moreover, Nvidia’s CUDA-X GPU-accelerated libraries are also at the disposal of Cadence and Samsung, helping accelerate EDA simulation and workloads to reduce the time it takes to verify designs. The simulations at 2nm are already quite compute-intensive, and the GPU-accelerated libraries make it easier for Cadence to deliver the product.