Alphawave Semi, an IP and contract chip designer, has developed the industry's first 3nm UCIe chiplet that enables die-to-die connectivity for system-in-packages made on TSMC's chip-on-wafer-on-substrate (CoWoS) packaging technology. The chiplet targets high-demand sectors such as hyperscalers, HPC, and AI, and allows users to build a wide range of system-in-packages (SiPs).
"Achieving successful silicon bring-up of 3nm 24 Gbps UCIe subsystem with TSMC's advanced packaging is a significant milestone for Alphawave Semi and underscores the company's expertise in utilizing the TSMC 3DFabric ecosystem to deliver top-tier connectivity solutions," said Mohit Gupta, Alphawave Semi’s SVP and GM of Custom Silicon and IP.
